1. Field of the Invention
This invention relates to an IC tester for testing the electrical properties of ICs (integral circuits).
2. Description of the Related Art
FIG. 2 shows a conventional IC tester for performing the so-called multi-testing, i.e., the simultaneous testing of a plurality of ICs. The IC tester shown has a prime oscillator 1 for generating reference signals and a timing circuit 2 connected to this prime oscillator 1. The timing circuit 2 includes a plurality of clock circuits 3 and a plurality of strobing circuits 4. The clock circuits 3 are connected to a plurality of selectors 6 through a distribution line 5 and the selectors 6 are connected to respective drivers 7. The strobing circuits 4 of the timing circuit 2 are connected to a plurality of selectors 8 through the distribution line 5 and the selectors 8 are connected to respective comparators 9. The drivers 7 and the comparators 9 are connected to respective tester pins 10.
Next, the operation of this IC tester when testing two ICs simultaneously will be described. First, the tester pins 10 are connected to the respective terminals of the two ICs 11 to be tested. Then, reference signals are supplied from the prime oscillator 1 to the clock circuits 3 and the strobing circuits 4, respectively, of the timing circuit 2. The clock circuits 3 then generate input timing signals of different timings and supply them to the selectors 6. The strobing circuits 4 generate judgment timing signals of different timings and supply them to the selectors 8.
The selectors 6 respectively select the requisite input timing signals in accordance with instructions from a CPU (not shown) and supply them to the corresponding drivers 7. The drivers 7 then generate testing signals on the basis of the input timing signals supplied to them and supply these testing signals to the respective input terminals of the ICs 11 through the tester pins 10. This causes the two ICs to operate in accordance with the respective testing signals supplied to them and emit output signals through their output terminals. These output signals are supplied to the corresponding comparators 9 through the tester pins 10. The selectors 8 select the requisite judgment timing signals in accordance with instructions from the CPU (not shown) and supply them to the corresponding comparators 9. The comparators 9 respectively make a judgment on the output signals from the ICs 11 on the basis of the judgment timing signals supplied, thereby deciding whether the ICs 11 are good or defective.
FIG. 3A shows the inner structure of an IC 11 which has been tested. The IC 11 shown is equipped with an internal circuit 12, which generates output signals on the basis of signals supplied to it through the input terminals 13 of this IC 11. The output signals are emitted through the output terminals 14 of the IC 11. At this time, an output signal S2 is emitted through one of the output terminals 14 with a delay of .DELTA.t with respect to the corresponding input signal S1, as shown in FIG. 3B, the delay .DELTA.t being always constant for the IC 11. Accordingly, the IC 11 can be tested correctly when the selectors 6 and 8 select proper input timing signals or proper judgment timing signals.
Further, a plurality of ICs 11 can be tested simultaneously under the same conditions if the same selectors 6 and the same drivers 7, or the same selectors 8 and the same comparators 9, are used for those terminals of the ICs 11 which have the same functions.
However, in the case of an IC used in a microcomputer or the like, i.e, an IC 15 which contains a special internal-clock generating circuit 16 as shown in FIG. 4A, a signal S3 supplied through the input terminal 17 of this IC 15 is divided by the internal-clock generating circuit 16 so as to form an internal clock signal Sc, and the internal circuit 18 of this IC 15 generates an output signal on the basis of this internal clock signal Sc. Thus, the internal circuit 18 operates with a special timing in accordance with the characteristics of the internal clock generating circuit 16, so that, as shown in FIG. 4B, the delay .DELTA.T of the output signal S4 emitted through the output terminal 19 with respect to the input signal S3 supplied to the input terminal 17 depends upon the timing of the internal clock signal Sc with respect to the input signal S3.
Therefore, an IC 15 which has an internal-clock generating circuit 16, as shown in in FIG. 4A, must be tested with a timing peculiar to this IC 15, which means it is difficult to test a plurality of such ICs simultaneously.